Verilog Fuzzer to test the major verilog compilers by generating random, valid Verilog. Resources are listed below:
- Verismith FPGA ’20 preprint
- Verismith thesis
- Verismith slides: Presented to the Circuits and Systems group at Imperial College on the 01/07/2019.
- Verismith poster: Presented at the Microsoft Research PhD Workshop on 25/11/2019.
It currently supports the following synthesisers:
and the following simulator:
Supported Verilog Constructs
The fuzzer generates combinational and behavioural Verilog to test the various tools. The most notable constructs that are supported and generated are the following:
- module definitions with parameter definitions, inputs and outputs
- module items, such as instantiations, continuous assignment, always blocks, initial blocks, parameter and local parameter declarations
- most expressions, for example concatenation, arithmetic operations, ternary conditional operator
- behavioural code in sequential always blocks
- behavioural control flow such as if-else and for loops
- declaration of wires and variables of any size, signed or unsigned
- bit selection from wires and variables
9 bugs have been reported and confirmed to be bugs by the vendors, out of which 4 have been fixed. 1 bug has also been found in the Icarus Verilog simulator as a side effect of using it to verify equivalence check results.