Hi! I’m currently a first year PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.

My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the Coq theorem prover called Vericert can be found on Github.

I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.

Publications

OOPSLA '21

Yann Herklotz, James D. Pollard, Nadesh Ramanathan, and John Wickerson. Formal verification of high-level synthesis. volume 5, New York, NY, USA, 11 2021. Association for Computing Machinery.
[ pdf ]

FCCM '21

Yann Herklotz, Zewei Du, Nadesh Ramanathan, and John Wickerson. An empirical study of the reliability of high-level synthesis tools. In 29th IEEE Annual Int. Symp. on Field-Programmable Custom Computing Machines, 2021.
[ DOI | artifact | pdf ]

FPGA '20

Yann Herklotz and John Wickerson. Finding and understanding bugs in FPGA synthesis tools. In ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 2020.
[ DOI | artifact | blog | pdf | poster | slides ]

Other Papers and Posters

LATTE '21

Yann Herklotz and John Wickerson. High-level synthesis tools should be proven correct. In Workshop on Languages, Tools, and Techniques for Accelerator Design, 2021.
[ pdf ]

FPGA '21

Zewei Du, Yann Herklotz, Nadesh Ramanathan, and John Wickerson. Fuzzing high-level synthesis tools. In ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 2021.
[ DOI | slides ]

Blog

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