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Hi! I’m currently a first year PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.

My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs).

I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.


FPGA '20
Yann Herklotz and John Wickerson. Finding and understanding bugs in FPGA synthesis tools. In ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 2020.
DOI | poster | slides | blog | pdf ]


MSR PhD Workshop on Next-Generation Cloud Infrastructure
Summary of the microsoft talks and posters presented at the MSR PhD Workshop on Next-Generation Cloud Infrastructure.
Verilog Fuzzer to test the major verilog compilers by generating random, valid Verilog.
Realistic Graphics
Jekyll to create a Portfolio website
Noise Silencer
Emotion Classification using Images
Emacs as an Email Client
C to MIPS32 Compiler