Hi! I’m currently a first year PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.
My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs).
I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.
2020-09-10 Artifact review committee at OOPSLA 2020. 2020-06-17 Gold medal at PLDI 2020 SRC Presentation. 2020-06-15 Student volunteer at PLDI 2020. 2019-12-15 FPGA 2020 Verismith paper accepted. 2019-07-15 Student volunteer at ECOOP 2019.